1. Field of the Invention
The present invention relates to semiconductor devices. More specifically, the present invention relates to routing signals within a semiconductor device.
2. Description of the Related Art
The current design of integrated circuits (IC) on semiconductor devices typically includes a multiple number of aluminum, aluminum alloy, copper, copper alloy, or tungsten layers separated by silicon dioxide insulators. Each layer comprises a complex pattern of metal wires across the surface of the layer. Connecting the layers together are metal wires or vias. The distance between the wires on a single layer of the IC and the distance between the layers determines the capacitance of each wire. Additionally, the width and height of each wire determines its conductivity (or inversely its resistance). The resistance times capacitance (RC) of a wire is a time constant that directly determines the time it takes to charge or discharge the capacitance of the wire.
An IC or logic circuit consumes power when conducting current through the wires either directly from the power pins to the ground pins or when charging or discharging a capacitor (within the circuit). Most power consumed within a CMOS circuit, however, comes from the charging/discharging of the capacitors. A capacitor in a logic circuit occurs due to the inherent capacitance of the metal wires that are within the circuit itself (i.e., inside the transistors and the wires in-between the transistors). Metal wires have capacitance that is a function of their surface area and their proximity to neighboring wires, while the capacitance of transistors is a function of their size. In other words, a logic circuit will consume more power if the circuit contains bigger transistors and or contains more wires or greater lengths of wire.
As the lithography improves and the spacing of wires gets closer together, their aspect ratio will change as shown in FIG. 1, which illustrates the capacitive coupling between neighboring signal wires in a semiconductor device and the capacitive coupling between adjacent layers by showing a cross-section of three metal layers. FIG. 1 additionally illustrates the current physical layout of an IC compared to a future IC layout. The height or the distance between layers will most likely remain unchanged as the width of the wires and spacing between the wires decreases. The wire height will most likely not decrease because a 50% reduction in both height and width would result in a wire with only 25% the conductivity, which is an unacceptable result for both signal and power routing. The spacing between layers can expect at best to be kept about the same. The relative distances between the conductors in the same layer will change, and this has an important impact on the signal carrying capabilities of the wires. As wires grow closer to their neighbors and relatively more distant from the conductors on adjacent layers, the ratio of capacitance between adjacent layers and neighbors will shift such that most of a wire's capacitive coupling will be to adjacent or neighboring wires.
If there was only a single wire on an IC, a designer would not care about a wire's capacitive coupling. Unfortunately, any given wire on an IC has neighboring wires and or adjacent wires that also carry signals. Since these other wires must carry signals, they are not held at static voltage levels. When a wire changes voltage, its charge capacitively couples to other wires in its vicinity and vice versa. A rising voltage on a wire will induce a rising voltage on a neighboring wire. If we were examining a wire and its neighboring wire transitions to a differing potential (i.e., the voltages are changing in opposite directions), we would see that the wire of interest would develop an induced charge that makes the wire's capacitance appear to increase. FIG. 1 illustrates the capacitive coupling of a wire with its neighboring wires and adjacent layer wires.
The degree of capacitive coupling between the two wires is the result of the amount of wire surface area each wire has in close proximity with the other wire. This amount of close wire surface area between wires is why there is a difference between neighbor capacitance and adjacent layer capacitance. Wires in adjacent layers run perpendicularly, which limits the common area between interlayer wires to a very small space, and directly limits any coupling effect, but wires in the same layer run next to each other for, potentially, their entire length, and can experience a dramatic coupling effect. As a result, except for uncommon cases, it is reasonable to assume there is no significant coupling between layers (interlayer coupling), while there is significant coupling within each layer (intralayer coupling).
Signal coupling is a problem for all integrated circuits because it degrades signal quality, alters signal propagation, and can cause logic failures. A design that tolerates signal coupling will require increased margins between wires, which directly reduces overall performance. The unfortunate fact is that technology is evolving to increase the amount of wire capacitance subject to coupling at the same time it is moving delay from the transistors into the wires. What used to be a minor annoyance for circuit designs has now become a major issue with interconnect. Improvements in dielectrics and conductors will help alleviate the problem, but it will continue to worsen as IC geometries shrink. Today's technology, when using the most aggressive metal spacing, has about two thirds of the total wire capacitance between neighbors, and within a few years this figure will be closer to three fourths.
With the prior art's problem with signal coupling, there exists a need to send information a given distance in an IC device with as low an effective capacitance as possible. Since signal coupling increases the effective capacitance of a datapath and or a logic device, reducing the signal coupling will improve the transmission of the information through the IC device. The present invention overcomes the signal coupling problem with a novel method and apparatus of routing a 1 of 4 signal to reduce the effective signal coupling between neighboring or adjacent layer signal wires. While routing the wires of a wire pack, the present invention rotates the route of each individual wire to reduce the signal coupling between the wires. The present invention also reduces the signal coupling when routing 1 of 3 signals and 1 of N signals.